# SystemVerilog GitHub repos

<https://repo.masters-masters.com/en/languages/systemverilog>

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All 157 SystemVerilog GitHub repos in RepoMasters, the trading card game of open source, most starred first: stars, tier and card for each.

## SystemVerilog GitHub repos

157 SystemVerilog repos in the catalog, most starred first.

- [adam-maj/tiny-gpu · ★ 13,161 · SystemVerilog · Stable](https://repo.masters-masters.com/en/repos/adam-maj/tiny-gpu)
- [verilator/verilator · ★ 4,049 · SystemVerilog · RC](https://repo.masters-masters.com/en/repos/verilator/verilator)
- [lowRISC/opentitan · ★ 3,725 · SystemVerilog · RC](https://repo.masters-masters.com/en/repos/lowRISC/opentitan)
- [lowRISC/ibex · ★ 2,148 · SystemVerilog · RC](https://repo.masters-masters.com/en/repos/lowRISC/ibex)
- [pulp-platform/axi · ★ 1,743 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/pulp-platform/axi)
- [aws/aws-fpga · ★ 1,691 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/aws/aws-fpga)
- [itsfrank/MinecraftHDL · ★ 1,596 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/itsfrank/MinecraftHDL)
- [hughperkins/VeriGPU · ★ 1,400 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/hughperkins/VeriGPU)
- [chili-chips-ba/wireguard-fpga · ★ 1,378 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/chili-chips-ba/wireguard-fpga)
- [openhwfoundation/cv32e40p · ★ 1,316 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/openhwfoundation/cv32e40p)
- [hdl-util/hdmi · ★ 1,308 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/hdl-util/hdmi)
- [rsd-devel/rsd · ★ 1,214 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/rsd-devel/rsd)
- [syntacore/scr1 · ★ 1,013 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/syntacore/scr1)
- [fpganinja/taxi · ★ 1,003 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/fpganinja/taxi)
- [chipsalliance/Cores-VeeR-EH1 · ★ 971 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/chipsalliance/Cores-VeeR-EH1)
- [westerndigitalcorporation/swerv\_eh1 · ★ 882 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/westerndigitalcorporation/swerv_eh1)
- [black-parrot/black-parrot · ★ 840 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/black-parrot/black-parrot)
- [pulp-platform/common\_cells · ★ 813 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/pulp-platform/common_cells)
- [projf/projf-explore · ★ 799 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/projf/projf-explore)
- [hwayne/lets-prove-leftpad · ★ 758 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/hwayne/lets-prove-leftpad)
- [bespoke-silicon-group/basejump\_stl · ★ 692 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/bespoke-silicon-group/basejump_stl)
- [raysalemi/uvmprimer · ★ 657 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/raysalemi/uvmprimer)
- [openhwfoundation/cvw · ★ 657 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/openhwfoundation/cvw)
- [openhwfoundation/cvfpu · ★ 647 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/openhwfoundation/cvfpu)
- [trivialmips/nontrivial-mips · ★ 609 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/trivialmips/nontrivial-mips)
- [lowRISC/lowrisc-chip · ★ 601 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/lowRISC/lowrisc-chip)
- [pulp-platform/pulp · ★ 572 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/pulp-platform/pulp)
- [pulp-platform/pulpissimo · ★ 501 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/pulp-platform/pulpissimo)
- [dpretet/async\_fifo · ★ 498 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/dpretet/async_fifo)
- [NVlabs/verilog-eval · ★ 491 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/NVlabs/verilog-eval)

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