# SystemVerilog GitHub repos, page 6

<https://repo.masters-masters.com/en/languages/systemverilog?page=6>

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All 155 SystemVerilog GitHub repos in RepoMasters, the trading card game of open source, most starred first: stars, tier and card for each. Page 6 of 6

## SystemVerilog GitHub repos, page 6

155 SystemVerilog repos in the catalog, most starred first.

- [YosysHQ/nerv · ★ 103 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/YosysHQ/nerv)
- [pulp-platform/tech\_cells\_generic · ★ 102 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/pulp-platform/tech_cells_generic)
- [chili-chips-ba/openeye-CamSI · ★ 102 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/chili-chips-ba/openeye-CamSI)
- [mirseo/JSilicon · ★ 101 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/mirseo/JSilicon)
- [pavona/pavona · ★ 101 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/pavona/pavona)

## Page 6 of 6

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Data: GitHub