# TL-Verilog GitHub repos

<https://repo.masters-masters.com/en/languages/tl-verilog>

[Home](https://repo.masters-masters.com/en) › [Languages](https://repo.masters-masters.com/en/languages) › [TL-Verilog](https://repo.masters-masters.com/en/languages/tl-verilog)

All 4 TL-Verilog GitHub repos in RepoMasters, the trading card game of open source, most starred first: stars, tier and card for each.

## TL-Verilog GitHub repos

4 TL-Verilog repos in the catalog, most starred first.

- [stevehoover/LF-Building-a-RISC-V-CPU-Core · ★ 519 · TL-Verilog · Alpha](https://repo.masters-masters.com/en/repos/stevehoover/LF-Building-a-RISC-V-CPU-Core)
- [os-fpga/Virtual-FPGA-Lab · ★ 284 · TL-Verilog · Alpha](https://repo.masters-masters.com/en/repos/os-fpga/Virtual-FPGA-Lab)
- [stevehoover/warp-v · ★ 257 · TL-Verilog · Alpha](https://repo.masters-masters.com/en/repos/stevehoover/warp-v)
- [stevehoover/RISC-V\_MYTH\_Workshop · ★ 105 · TL-Verilog · Prototype](https://repo.masters-masters.com/en/repos/stevehoover/RISC-V_MYTH_Workshop)

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Data: GitHub