# Verilog GitHub repos [Home](https://repo.masters-masters.com/en) › [Languages](https://repo.masters-masters.com/en/languages) › [Verilog](https://repo.masters-masters.com/en/languages/verilog) All 427 Verilog GitHub repos in RepoMasters, the trading card game of open source, most starred first: stars, tier and card for each. ## Verilog GitHub repos 427 Verilog repos in the catalog, most starred first. - [YosysHQ/picorv32 · ★ 4,397 · Verilog · RC](https://repo.masters-masters.com/en/repos/YosysHQ/picorv32) - [The-OpenROAD-Project/OpenROAD · ★ 3,250 · Verilog · RC](https://repo.masters-masters.com/en/repos/The-OpenROAD-Project/OpenROAD) - [alexforencich/verilog-ethernet · ★ 3,143 · Verilog · RC](https://repo.masters-masters.com/en/repos/alexforencich/verilog-ethernet) - [SI-RISCV/e200\_opensource · ★ 2,855 · Verilog · RC](https://repo.masters-masters.com/en/repos/SI-RISCV/e200_opensource) - [darklife/darkriscv · ★ 2,632 · Verilog · RC](https://repo.masters-masters.com/en/repos/darklife/darkriscv) - [corundum/corundum · ★ 2,508 · Verilog · RC](https://repo.masters-masters.com/en/repos/corundum/corundum) - [vortexgpgpu/vortex · ★ 2,373 · Verilog · RC](https://repo.masters-masters.com/en/repos/vortexgpgpu/vortex) - [nvdla/hw · ★ 2,195 · Verilog · RC](https://repo.masters-masters.com/en/repos/nvdla/hw) - [alexforencich/verilog-axi · ★ 2,168 · Verilog · RC](https://repo.masters-masters.com/en/repos/alexforencich/verilog-axi) - [XUANTIE-RV/wujian100\_open · ★ 2,031 · Verilog · RC](https://repo.masters-masters.com/en/repos/XUANTIE-RV/wujian100_open) - [pConst/basic\_verilog · ★ 2,030 · Verilog · RC](https://repo.masters-masters.com/en/repos/pConst/basic_verilog) - [riscv-mcu/e203\_hbirdv2 · ★ 1,970 · Verilog · Beta](https://repo.masters-masters.com/en/repos/riscv-mcu/e203_hbirdv2) - [olofk/serv · ★ 1,914 · Verilog · Beta](https://repo.masters-masters.com/en/repos/olofk/serv) - [ufrisk/pcileech-fpga · ★ 1,850 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ufrisk/pcileech-fpga) - [ultraembedded/riscv · ★ 1,812 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ultraembedded/riscv) - [alexforencich/verilog-pcie · ★ 1,675 · Verilog · Beta](https://repo.masters-masters.com/en/repos/alexforencich/verilog-pcie) - [ZipCPU/zipcpu · ★ 1,597 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ZipCPU/zipcpu) - [XUANTIE-RV/openc910 · ★ 1,490 · Verilog · Beta](https://repo.masters-masters.com/en/repos/XUANTIE-RV/openc910) - [aolofsson/oh · ★ 1,440 · Verilog · Beta](https://repo.masters-masters.com/en/repos/aolofsson/oh) - [VerticalResearchGroup/miaow · ★ 1,431 · Verilog · Beta](https://repo.masters-masters.com/en/repos/VerticalResearchGroup/miaow) - [tiny-tpu-v2/tiny-tpu · ★ 1,411 · Verilog · Beta](https://repo.masters-masters.com/en/repos/tiny-tpu-v2/tiny-tpu) - [ultraembedded/biriscv · ★ 1,329 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ultraembedded/biriscv) - [EttusResearch/uhd · ★ 1,295 · Verilog · Beta](https://repo.masters-masters.com/en/repos/EttusResearch/uhd) - [Digital-EDA/Digital-IDE · ★ 1,191 · Verilog · Beta](https://repo.masters-masters.com/en/repos/Digital-EDA/Digital-IDE) - [circuitvalley/USB\_C\_Industrial\_Camera\_FPGA\_USB3 · ★ 1,170 · Verilog · Beta](https://repo.masters-masters.com/en/repos/circuitvalley/USB_C_Industrial_Camera_FPGA_USB3) - [lnis-uofu/OpenFPGA · ★ 1,166 · Verilog · Beta](https://repo.masters-masters.com/en/repos/lnis-uofu/OpenFPGA) - [Wren6991/Hazard3 · ★ 1,131 · Verilog · Beta](https://repo.masters-masters.com/en/repos/Wren6991/Hazard3) - [splinedrive/kianRiscV · ★ 1,123 · Verilog · Beta](https://repo.masters-masters.com/en/repos/splinedrive/kianRiscV) - [odriverobotics/ODriveHardware · ★ 1,110 · Verilog · Beta](https://repo.masters-masters.com/en/repos/odriverobotics/ODriveHardware) - [mntmn/amiga2000-gfxcard · ★ 1,021 · Verilog · Beta](https://repo.masters-masters.com/en/repos/mntmn/amiga2000-gfxcard) ## Page 1 of 15 - [Next page](https://repo.masters-masters.com/en/languages/verilog?page=2) --- Data: GitHub