# Verilog GitHub repos, page 11

<https://repo.masters-masters.com/en/languages/verilog?page=11>

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All 427 Verilog GitHub repos in RepoMasters, the trading card game of open source, most starred first: stars, tier and card for each. Page 11 of 15

## Verilog GitHub repos, page 11

427 Verilog repos in the catalog, most starred first.

- [mattvenn/basic-ecp5-pcb · ★ 144 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/mattvenn/basic-ecp5-pcb)
- [racerxdl/riskow · ★ 144 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/racerxdl/riskow)
- [MoonshotAI/nano-kpu · ★ 144 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/MoonshotAI/nano-kpu)
- [abdelazeem201/Cadence-RTL-to-GDSII-Flow · ★ 141 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/abdelazeem201/Cadence-RTL-to-GDSII-Flow)
- [Azalea8/riscv\_cpu · ★ 141 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/Azalea8/riscv_cpu)
- [RongyeL/EasyAXI · ★ 141 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/RongyeL/EasyAXI)
- [MiSTer-devel/Gameboy\_MiSTer · ★ 140 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/MiSTer-devel/Gameboy_MiSTer)
- [WangXuan95/FPGA-SDfake · ★ 140 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-SDfake)
- [HDLForBeginners/Examples · ★ 140 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/HDLForBeginners/Examples)
- [russdill/bch\_verilog · ★ 139 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/russdill/bch_verilog)
- [AngeloJacobo/RISC-V · ★ 139 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/AngeloJacobo/RISC-V)
- [open-fpga/core-template · ★ 139 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/open-fpga/core-template)
- [efabless/caravel\_mpw-one · ★ 138 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/efabless/caravel_mpw-one)
- [NXP/i3c-slave-design · ★ 137 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/NXP/i3c-slave-design)
- [mczerski/SD-card-controller · ★ 136 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/mczerski/SD-card-controller)
- [rj45/rj32 · ★ 136 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/rj45/rj32)
- [virtualagc/agc\_simulation · ★ 135 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/virtualagc/agc_simulation)
- [ekb0412/100DaysofRTL · ★ 135 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/ekb0412/100DaysofRTL)
- [airin711/Verilog-caches · ★ 134 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/airin711/Verilog-caches)
- [Daniel-GGB/My-Digital-IC-Library · ★ 134 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/Daniel-GGB/My-Digital-IC-Library)
- [AugustinJose1221/FPGA-Build · ★ 134 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/AugustinJose1221/FPGA-Build)
- [robinhedwards/UltimateCart · ★ 133 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/robinhedwards/UltimateCart)
- [ZipCPU/openarty · ★ 133 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/ZipCPU/openarty)
- [exeex/edge-cores · ★ 133 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/exeex/edge-cores)
- [MiSTer-devel/Genesis\_MiSTer · ★ 132 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/MiSTer-devel/Genesis_MiSTer)
- [circuitgraph/circuitgraph · ★ 132 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/circuitgraph/circuitgraph)
- [phoeniX-Digital-Design/phoeniX · ★ 132 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/phoeniX-Digital-Design/phoeniX)
- [mole99/gf180mcu-fabulous-fpga · ★ 132 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/mole99/gf180mcu-fabulous-fpga)
- [jotego/jt12 · ★ 131 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/jotego/jt12)
- [Trinkle23897/mips32-cpu · ★ 131 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/Trinkle23897/mips32-cpu)

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