# Verilog GitHub repos, page 2 [Home](https://repo.masters-masters.com/en) › [Languages](https://repo.masters-masters.com/en/languages) › [Verilog](https://repo.masters-masters.com/en/languages/verilog) All 427 Verilog GitHub repos in RepoMasters, the trading card game of open source, most starred first: stars, tier and card for each. Page 2 of 15 ## Verilog GitHub repos, page 2 427 Verilog repos in the catalog, most starred first. - [WangXuan95/FPGA-FOC · ★ 994 · Verilog · Beta](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-FOC) - [ultraembedded/cores · ★ 940 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ultraembedded/cores) - [WangXuan95/FPGA-USB-Device · ★ 934 · Verilog · Beta](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-USB-Device) - [open-sdr/openwifi-hw · ★ 917 · Verilog · Beta](https://repo.masters-masters.com/en/repos/open-sdr/openwifi-hw) - [FeSens/openTPU · ★ 907 · Verilog · Beta](https://repo.masters-masters.com/en/repos/FeSens/openTPU) - [lvyufeng/step\_into\_mips · ★ 886 · Verilog · Beta](https://repo.masters-masters.com/en/repos/lvyufeng/step_into_mips) - [KastnerRG/riffa · ★ 884 · Verilog · Beta](https://repo.masters-masters.com/en/repos/KastnerRG/riffa) - [Obijuan/open-fpga-verilog-tutorial · ★ 871 · Verilog · Beta](https://repo.masters-masters.com/en/repos/Obijuan/open-fpga-verilog-tutorial) - [xiaop1/Verilog-Practice · ★ 818 · Verilog · Beta](https://repo.masters-masters.com/en/repos/xiaop1/Verilog-Practice) - [rejunity/z80-open-silicon · ★ 814 · Verilog · Beta](https://repo.masters-masters.com/en/repos/rejunity/z80-open-silicon) - [ekknod/pcileech-wifi · ★ 793 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ekknod/pcileech-wifi) - [The-OpenROAD-Project/OpenROAD-flow-scripts · ★ 791 · Verilog · Beta](https://repo.masters-masters.com/en/repos/The-OpenROAD-Project/OpenROAD-flow-scripts) - [Luthiraa/TALOS-V2 · ★ 785 · Verilog · Beta](https://repo.masters-masters.com/en/repos/Luthiraa/TALOS-V2) - [dawsonjon/fpu · ★ 763 · Verilog · Beta](https://repo.masters-masters.com/en/repos/dawsonjon/fpu) - [alexforencich/verilog-i2c · ★ 731 · Verilog · Beta](https://repo.masters-masters.com/en/repos/alexforencich/verilog-i2c) - [antonblanchard/microwatt · ★ 730 · Verilog · Beta](https://repo.masters-masters.com/en/repos/antonblanchard/microwatt) - [OpenTimer/OpenTimer · ★ 722 · Verilog · Beta](https://repo.masters-masters.com/en/repos/OpenTimer/OpenTimer) - [ZipCPU/wb2axip · ★ 714 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ZipCPU/wb2axip) - [jmahler/mips-cpu · ★ 660 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/jmahler/mips-cpu) - [fguzman82/gateGPT · ★ 656 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/fguzman82/gateGPT) - [ultraembedded/core\_ddr3\_controller · ★ 646 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/ultraembedded/core_ddr3_controller) - [dtysky/FPGA-Imaging-Library · ★ 644 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/dtysky/FPGA-Imaging-Library) - [The-OpenROAD-Project/OpenSTA · ★ 639 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/The-OpenROAD-Project/OpenSTA) - [SymbioticEDA/riscv-formal · ★ 634 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/SymbioticEDA/riscv-formal) - [seldridge/verilog · ★ 632 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/seldridge/verilog) - [danielholanda/LeFlow · ★ 630 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/danielholanda/LeFlow) - [omarelhedaby/CNN-FPGA · ★ 614 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/omarelhedaby/CNN-FPGA) - [QShen3/CNN-FPGA · ★ 595 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/QShen3/CNN-FPGA) - [openrisc/mor1kx · ★ 594 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/openrisc/mor1kx) - [sheldonucr/ucr-eecs168-lab · ★ 593 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/sheldonucr/ucr-eecs168-lab) ## Page 2 of 15 - [Previous page](https://repo.masters-masters.com/en/languages/verilog) - [Next page](https://repo.masters-masters.com/en/languages/verilog?page=3) --- Data: GitHub