# VHDL GitHub repos, page 5 [Home](https://repo.masters-masters.com/en) › [Languages](https://repo.masters-masters.com/en/languages) › [VHDL](https://repo.masters-masters.com/en/languages/vhdl) All 140 VHDL GitHub repos in RepoMasters, the trading card game of open source, most starred first: stars, tier and card for each. Page 5 of 5 ## VHDL GitHub repos, page 5 140 VHDL repos in the catalog, most starred first. - [hoglet67/AtomBusMon · ★ 109 · VHDL · Prototype](https://repo.masters-masters.com/en/repos/hoglet67/AtomBusMon) - [timvideos/HDMI2USB-jahanzeb-firmware · ★ 108 · VHDL · Prototype](https://repo.masters-masters.com/en/repos/timvideos/HDMI2USB-jahanzeb-firmware) - [texane/vpcie · ★ 108 · VHDL · Prototype](https://repo.masters-masters.com/en/repos/texane/vpcie) - [MiSTer-devel/TurboGrafx16\_MiSTer · ★ 108 · VHDL · Prototype](https://repo.masters-masters.com/en/repos/MiSTer-devel/TurboGrafx16_MiSTer) - [MiSTer-devel/N64\_MiSTer · ★ 108 · VHDL · Prototype](https://repo.masters-masters.com/en/repos/MiSTer-devel/N64_MiSTer) - [stiggy87/ZynqBTC · ★ 107 · VHDL · Prototype](https://repo.masters-masters.com/en/repos/stiggy87/ZynqBTC) - [endofexclusive/greta · ★ 107 · VHDL · Prototype](https://repo.masters-masters.com/en/repos/endofexclusive/greta) - [madcowswe/ODriveFPGA · ★ 107 · VHDL · Prototype](https://repo.masters-masters.com/en/repos/madcowswe/ODriveFPGA) - [stnolting/captouch · ★ 106 · VHDL · Prototype](https://repo.masters-masters.com/en/repos/stnolting/captouch) - [Gralerfics/FmcPGA · ★ 106 · VHDL · Prototype](https://repo.masters-masters.com/en/repos/Gralerfics/FmcPGA) - [Xilinx/IIoT-EDDP · ★ 105 · VHDL · Prototype](https://repo.masters-masters.com/en/repos/Xilinx/IIoT-EDDP) - [I-CAN-hack/flexray-interceptor · ★ 105 · VHDL · Prototype](https://repo.masters-masters.com/en/repos/I-CAN-hack/flexray-interceptor) - [endofexclusive/deniser · ★ 105 · VHDL · Prototype](https://repo.masters-masters.com/en/repos/endofexclusive/deniser) - [Digilent/Basys3 · ★ 104 · VHDL · Prototype](https://repo.masters-masters.com/en/repos/Digilent/Basys3) - [Futuresxy/General-CNN-Accelerator · ★ 104 · VHDL · Prototype](https://repo.masters-masters.com/en/repos/Futuresxy/General-CNN-Accelerator) - [OldGlycine/BJUT-CS · ★ 104 · VHDL · Prototype](https://repo.masters-masters.com/en/repos/OldGlycine/BJUT-CS) - [inmcm/Simon\_Speck\_Ciphers · ★ 103 · VHDL · Prototype](https://repo.masters-masters.com/en/repos/inmcm/Simon_Speck_Ciphers) - [mincer-ray/openfpga-GBA · ★ 103 · VHDL · Prototype](https://repo.masters-masters.com/en/repos/mincer-ray/openfpga-GBA) - [stnolting/neorv32-setups · ★ 102 · VHDL · Prototype](https://repo.masters-masters.com/en/repos/stnolting/neorv32-setups) - [stnolting/neorv32-verilog · ★ 101 · VHDL · Prototype](https://repo.masters-masters.com/en/repos/stnolting/neorv32-verilog) ## Page 5 of 5 - [Previous page](https://repo.masters-masters.com/en/languages/vhdl?page=4) --- Data: GitHub