# GitHub repos by chipsalliance

<https://repo.masters-masters.com/en/owners/chipsalliance>

[Home](https://repo.masters-masters.com/en) › [chipsalliance](https://repo.masters-masters.com/en/owners/chipsalliance)

All 29 public GitHub repos by chipsalliance in RepoMasters, most starred first: stars, language, tier and card for each.

## GitHub repos by chipsalliance

29 public repos by chipsalliance in the catalog, most starred first.

- [chipsalliance/chisel · ★ 4,827 · Scala · RC](https://repo.masters-masters.com/en/repos/chipsalliance/chisel)
- [chipsalliance/rocket-chip · ★ 3,895 · Scala · RC](https://repo.masters-masters.com/en/repos/chipsalliance/rocket-chip)
- [chipsalliance/verible · ★ 1,974 · C++ · Beta](https://repo.masters-masters.com/en/repos/chipsalliance/verible)
- [chipsalliance/riscv-dv · ★ 1,375 · Python · Beta](https://repo.masters-masters.com/en/repos/chipsalliance/riscv-dv)
- [chipsalliance/Cores-VeeR-EH1 · ★ 971 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/chipsalliance/Cores-VeeR-EH1)
- [chipsalliance/firrtl · ★ 748 · Scala · Beta](https://repo.masters-masters.com/en/repos/chipsalliance/firrtl)
- [chipsalliance/chisel-template · ★ 709 · Shell · Beta](https://repo.masters-masters.com/en/repos/chipsalliance/chisel-template)
- [chipsalliance/Caliptra · ★ 485 · Alpha](https://repo.masters-masters.com/en/repos/chipsalliance/Caliptra)
- [chipsalliance/Surelog · ★ 476 · C++ · Alpha](https://repo.masters-masters.com/en/repos/chipsalliance/Surelog)
- [chipsalliance/f4pga · ★ 453 · Python · Alpha](https://repo.masters-masters.com/en/repos/chipsalliance/f4pga)
- [chipsalliance/sv-tests · ★ 406 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/chipsalliance/sv-tests)
- [chipsalliance/Cores-VeeR-EL2 · ★ 349 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/chipsalliance/Cores-VeeR-EL2)
- [chipsalliance/VeeRwolf · ★ 343 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/chipsalliance/VeeRwolf)
- [chipsalliance/t1 · ★ 325 · Scala · Alpha](https://repo.masters-masters.com/en/repos/chipsalliance/t1)
- [chipsalliance/f4pga-examples · ★ 290 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/chipsalliance/f4pga-examples)
- [chipsalliance/Cores-VeeR-EH2 · ★ 283 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/chipsalliance/Cores-VeeR-EH2)
- [chipsalliance/UHDM · ★ 269 · C++ · Alpha](https://repo.masters-masters.com/en/repos/chipsalliance/UHDM)
- [chipsalliance/dromajo · ★ 244 · C++ · Prototype](https://repo.masters-masters.com/en/repos/chipsalliance/dromajo)
- [chipsalliance/synlig · ★ 237 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/chipsalliance/synlig)
- [chipsalliance/silicon-notebooks · ★ 178 · Jupyter Notebook · Prototype](https://repo.masters-masters.com/en/repos/chipsalliance/silicon-notebooks)
- [chipsalliance/caliptra-sw · ★ 172 · Rust · Prototype](https://repo.masters-masters.com/en/repos/chipsalliance/caliptra-sw)
- [chipsalliance/caliptra-rtl · ★ 160 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/chipsalliance/caliptra-rtl)
- [chipsalliance/VeeR-ISS · ★ 158 · C++ · Prototype](https://repo.masters-masters.com/en/repos/chipsalliance/VeeR-ISS)
- [chipsalliance/treadle · ★ 157 · Scala · Prototype](https://repo.masters-masters.com/en/repos/chipsalliance/treadle)
- [chipsalliance/aib-phy-hardware · ★ 151 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/chipsalliance/aib-phy-hardware)
- [chipsalliance/uvm-verilator · ★ 143 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/chipsalliance/uvm-verilator)
- [chipsalliance/riscv-vector-tests · ★ 118 · Go · Prototype](https://repo.masters-masters.com/en/repos/chipsalliance/riscv-vector-tests)
- [chipsalliance/fpga-tool-perf · ★ 108 · Python · Prototype](https://repo.masters-masters.com/en/repos/chipsalliance/fpga-tool-perf)
- [chipsalliance/fasm · ★ 103 · Python · Prototype](https://repo.masters-masters.com/en/repos/chipsalliance/fasm)

## See chipsalliance on GitHub

- [https://github.com/chipsalliance](https://github.com/chipsalliance)

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Data: GitHub