# GitHub repos by ultraembedded

<https://repo.masters-masters.com/en/owners/ultraembedded>

[Home](https://repo.masters-masters.com/en) › [ultraembedded](https://repo.masters-masters.com/en/owners/ultraembedded)

All 14 public GitHub repos by ultraembedded in RepoMasters, most starred first: stars, language, tier and card for each.

## GitHub repos by ultraembedded

14 public repos by ultraembedded in the catalog, most starred first.

- [ultraembedded/riscv · ★ 1,812 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ultraembedded/riscv)
- [ultraembedded/biriscv · ★ 1,329 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ultraembedded/biriscv)
- [ultraembedded/cores · ★ 940 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ultraembedded/cores)
- [ultraembedded/core\_ddr3\_controller · ★ 645 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/ultraembedded/core_ddr3_controller)
- [ultraembedded/FPGAmp · ★ 307 · C · Alpha](https://repo.masters-masters.com/en/repos/ultraembedded/FPGAmp)
- [ultraembedded/core\_jpeg · ★ 283 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/ultraembedded/core_jpeg)
- [ultraembedded/riscv\_soc · ★ 213 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/ultraembedded/riscv_soc)
- [ultraembedded/openlogicbit · ★ 178 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/ultraembedded/openlogicbit)
- [ultraembedded/exactstep · ★ 114 · C++ · Prototype](https://repo.masters-masters.com/en/repos/ultraembedded/exactstep)
- [ultraembedded/libhelix-mp3 · ★ 113 · C · Prototype](https://repo.masters-masters.com/en/repos/ultraembedded/libhelix-mp3)
- [ultraembedded/core\_sdram\_axi4 · ★ 110 · C++ · Prototype](https://repo.masters-masters.com/en/repos/ultraembedded/core_sdram_axi4)
- [ultraembedded/core\_ft60x\_axi · ★ 104 · C++ · Prototype](https://repo.masters-masters.com/en/repos/ultraembedded/core_ft60x_axi)
- [ultraembedded/core\_usb\_host · ★ 103 · C · Prototype](https://repo.masters-masters.com/en/repos/ultraembedded/core_usb_host)
- [ultraembedded/core\_audio · ★ 101 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/ultraembedded/core_audio)

## See ultraembedded on GitHub

- [https://github.com/ultraembedded](https://github.com/ultraembedded)

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Data: GitHub