# AngeloJacobo/RISC-V

<https://repo.masters-masters.com/en/repos/AngeloJacobo/RISC-V>

[Home](https://repo.masters-masters.com/en) › [AngeloJacobo](https://repo.masters-masters.com/en/owners/AngeloJacobo) › [RISC-V](https://repo.masters-masters.com/en/repos/AngeloJacobo/RISC-V)

AngeloJacobo/RISC-V has 139 stars on GitHub. Its RepoMasters card: Prototype tier. Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

| Field | Value |
| --- | --- |
| Owner | [AngeloJacobo](https://repo.masters-masters.com/en/owners/AngeloJacobo) |
| Stars | 139 |
| Forks | 11 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | MIT |
| Created | 2022 |
| Topics | risc-v, verilog, rv32i, rv32, cpu, riscv, 5-stage-pipeline, formal-verification |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [AngeloJacobo/RISC-V](https://github.com/AngeloJacobo/RISC-V) |

## Repository

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by AngeloJacobo

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.