# Arlet/verilog-6502

<https://repo.masters-masters.com/en/repos/Arlet/verilog-6502>

[Home](https://repo.masters-masters.com/en) › [Arlet](https://repo.masters-masters.com/en/owners/Arlet) › [verilog-6502](https://repo.masters-masters.com/en/repos/Arlet/verilog-6502)

Arlet/verilog-6502 has 391 stars on GitHub. Its RepoMasters card: Alpha tier. A Verilog HDL model of the MOS 6502 CPU Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [Arlet](https://repo.masters-masters.com/en/owners/Arlet) |
| Stars | 391 |
| Forks | 108 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | None |
| Created | 2011 |
| Tier | [Alpha (250 to 699 ★)](https://repo.masters-masters.com/en/ranks/b_movie) |
| View on GitHub | [Arlet/verilog-6502](https://github.com/Arlet/verilog-6502) |

## Repository

A Verilog HDL model of the MOS 6502 CPU

The tier for repos with 250 to 699 ★. Published odds per card pulled: 20%. Rarity: Uncommon.

## Nearby in Verilog

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- [Evensgn/RISC-V-CPU · ★ 392 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/Evensgn/RISC-V-CPU)
- [stffrdhrn/sdram-controller · ★ 389 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/stffrdhrn/sdram-controller)
- [ridecore/ridecore · ★ 387 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/ridecore/ridecore)
- [pulp-platform/cheshire · ★ 385 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/pulp-platform/cheshire)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.