# Azalea8/riscv\_cpu

<https://repo.masters-masters.com/en/repos/Azalea8/riscv_cpu>

[Home](https://repo.masters-masters.com/en) › [Azalea8](https://repo.masters-masters.com/en/owners/Azalea8) › [riscv\_cpu](https://repo.masters-masters.com/en/repos/Azalea8/riscv_cpu)

Azalea8/riscv\_cpu has 141 stars on GitHub. Its RepoMasters card: Prototype tier. riscv指令集，单周期以及五级流水线CPU Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [Azalea8](https://repo.masters-masters.com/en/owners/Azalea8) |
| Stars | 141 |
| Forks | 17 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | None |
| Created | 2024 |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [Azalea8/riscv\_cpu](https://github.com/Azalea8/riscv_cpu) |

## Repository

riscv指令集，单周期以及五级流水线CPU

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## Nearby in Verilog

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- [WangXuan95/FPGA-SDfake · ★ 140 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-SDfake)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.
