# Digital-EDA/Digital-IDE

<https://repo.masters-masters.com/en/repos/Digital-EDA/Digital-IDE>

[Home](https://repo.masters-masters.com/en) › [Digital-EDA](https://repo.masters-masters.com/en/owners/Digital-EDA) › [Digital-IDE](https://repo.masters-masters.com/en/repos/Digital-EDA/Digital-IDE)

Digital-EDA/Digital-IDE has 1,191 stars on GitHub. Its RepoMasters card: Beta tier. All in one vscode plugin for HDL development Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [Digital-EDA](https://repo.masters-masters.com/en/owners/Digital-EDA) |
| Stars | 1,191 |
| Forks | 71 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | MIT |
| Created | 2023 |
| Tier | [Beta (700 to 1,999 ★)](https://repo.masters-masters.com/en/ranks/box_office) |
| View on GitHub | [Digital-EDA/Digital-IDE](https://github.com/Digital-EDA/Digital-IDE) |

## Repository

All in one vscode plugin for HDL development

The tier for repos with 700 to 1,999 ★. Published odds per card pulled: 6%. Rarity: Rare.

## Nearby in Verilog

- [tiny-tpu-v2/tiny-tpu · ★ 1,412 · Verilog · Beta](https://repo.masters-masters.com/en/repos/tiny-tpu-v2/tiny-tpu)
- [ultraembedded/biriscv · ★ 1,329 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ultraembedded/biriscv)
- [EttusResearch/uhd · ★ 1,296 · Verilog · Beta](https://repo.masters-masters.com/en/repos/EttusResearch/uhd)
- [circuitvalley/USB\_C\_Industrial\_Camera\_FPGA\_USB3 · ★ 1,170 · Verilog · Beta](https://repo.masters-masters.com/en/repos/circuitvalley/USB_C_Industrial_Camera_FPGA_USB3)
- [lnis-uofu/OpenFPGA · ★ 1,167 · Verilog · Beta](https://repo.masters-masters.com/en/repos/lnis-uofu/OpenFPGA)
- [Wren6991/Hazard3 · ★ 1,131 · Verilog · Beta](https://repo.masters-masters.com/en/repos/Wren6991/Hazard3)

---
Data: GitHub · Illustration: the project’s public image, pixelated by RepoMasters.
