# DreamSourceLab/DSLogic-hdl

<https://repo.masters-masters.com/en/repos/DreamSourceLab/DSLogic-hdl>

[Home](https://repo.masters-masters.com/en) › [DreamSourceLab](https://repo.masters-masters.com/en/owners/DreamSourceLab) › [DSLogic-hdl](https://repo.masters-masters.com/en/repos/DreamSourceLab/DSLogic-hdl)

DreamSourceLab/DSLogic-hdl has 177 stars on GitHub. Its RepoMasters card: Prototype tier. An open source FPGA design for DSLogic Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [DreamSourceLab](https://repo.masters-masters.com/en/owners/DreamSourceLab) |
| Stars | 177 |
| Forks | 83 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | GPL-2.0 |
| Created | 2014 |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [DreamSourceLab/DSLogic-hdl](https://github.com/DreamSourceLab/DSLogic-hdl) |

## Repository

An open source FPGA design for DSLogic

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by DreamSourceLab

- [DreamSourceLab/DSView · ★ 1,445 · Python · Beta](https://repo.masters-masters.com/en/repos/DreamSourceLab/DSView)
- [DreamSourceLab/DSLogic-fw · ★ 109 · C · Prototype](https://repo.masters-masters.com/en/repos/DreamSourceLab/DSLogic-fw)

## Nearby in Verilog

- [lamda-bbo/Open3DBench · ★ 179 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/lamda-bbo/Open3DBench)
- [denandz/lpc\_sniffer\_tpm · ★ 178 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/denandz/lpc_sniffer_tpm)
- [ultraembedded/openlogicbit · ★ 178 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/ultraembedded/openlogicbit)
- [mustafabbas/ECE1373\_2016\_hft\_on\_fpga · ★ 176 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/mustafabbas/ECE1373_2016_hft_on_fpga)
- [MiSTer-devel/NeoGeo\_MiSTer · ★ 176 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/MiSTer-devel/NeoGeo_MiSTer)
- [AUCOHL/DFFRAM · ★ 176 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/AUCOHL/DFFRAM)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.