# Evensgn/RISC-V-CPU

<https://repo.masters-masters.com/en/repos/Evensgn/RISC-V-CPU>

[Home](https://repo.masters-masters.com/en) › [Evensgn](https://repo.masters-masters.com/en/owners/Evensgn) › [RISC-V-CPU](https://repo.masters-masters.com/en/repos/Evensgn/RISC-V-CPU)

Evensgn/RISC-V-CPU has 392 stars on GitHub. Its RepoMasters card: Alpha tier. RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL. Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [Evensgn](https://repo.masters-masters.com/en/owners/Evensgn) |
| Stars | 392 |
| Forks | 52 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | None |
| Created | 2017 |
| Tier | [Alpha (250 to 699 ★)](https://repo.masters-masters.com/en/ranks/b_movie) |
| View on GitHub | [Evensgn/RISC-V-CPU](https://github.com/Evensgn/RISC-V-CPU) |

## Repository

RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.

The tier for repos with 250 to 699 ★. Published odds per card pulled: 20%. Rarity: Uncommon.

## Nearby in Verilog

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- [Arlet/verilog-6502 · ★ 391 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/Arlet/verilog-6502)
- [stffrdhrn/sdram-controller · ★ 389 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/stffrdhrn/sdram-controller)
- [ridecore/ridecore · ★ 387 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/ridecore/ridecore)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.