# FPGADude/Digital-Design

<https://repo.masters-masters.com/en/repos/FPGADude/Digital-Design>

[Home](https://repo.masters-masters.com/en) › [FPGADude](https://repo.masters-masters.com/en/owners/FPGADude) › [Digital-Design](https://repo.masters-masters.com/en/repos/FPGADude/Digital-Design)

FPGADude/Digital-Design has 193 stars on GitHub. Its RepoMasters card: Prototype tier. Verilog HDL files Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [FPGADude](https://repo.masters-masters.com/en/owners/FPGADude) |
| Stars | 193 |
| Forks | 63 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | GPL-3.0 |
| Created | 2021 |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [FPGADude/Digital-Design](https://github.com/FPGADude/Digital-Design) |

## Repository

Verilog HDL files

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## Nearby in Verilog

- [hrvach/fpg1 · ★ 195 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/hrvach/fpg1)
- [ulixxe/usb\_cdc · ★ 194 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/ulixxe/usb_cdc)
- [muditbhargava66/High-Frequency-Trading-FPGA-System · ★ 194 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/muditbhargava66/High-Frequency-Trading-FPGA-System)
- [bluespec/Toooba · ★ 192 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/bluespec/Toooba)
- [MiSTer-devel/Minimig-AGA\_MiSTer · ★ 191 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/MiSTer-devel/Minimig-AGA_MiSTer)
- [ZFTurbo/MobileNet-in-FPGA · ★ 191 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/ZFTurbo/MobileNet-in-FPGA)

---
Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.