# Juniper/open-register-design-tool

<https://repo.masters-masters.com/en/repos/Juniper/open-register-design-tool>

[Home](https://repo.masters-masters.com/en) › [Juniper](https://repo.masters-masters.com/en/owners/Juniper) › [open-register-design-tool](https://repo.masters-masters.com/en/repos/Juniper/open-register-design-tool)

Juniper/open-register-design-tool has 209 stars on GitHub. Its RepoMasters card: Prototype tier. Tool to generate register RTL, models, and docs using…

| Field | Value |
| --- | --- |
| Owner | [Juniper](https://repo.masters-masters.com/en/owners/Juniper) |
| Stars | 209 |
| Forks | 74 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | Apache-2.0 |
| Created | 2016 |
| Topics | systemrdl, jspec, eda, asic, fpga, registers, uvm, systemverilog, register-descriptions, systemrdl-compiler |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [Juniper/open-register-design-tool](https://github.com/Juniper/open-register-design-tool) |

## Repository

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.