# MPSU/APS

<https://repo.masters-masters.com/en/repos/MPSU/APS>

[Home](https://repo.masters-masters.com/en) › [MPSU](https://repo.masters-masters.com/en/owners/MPSU) › [APS](https://repo.masters-masters.com/en/repos/MPSU/APS)

MPSU/APS has 362 stars on GitHub. Its RepoMasters card: Alpha tier. Laboratory course on RISC-V Processor Development Language: SystemVerilog.

| Field | Value |
| --- | --- |
| Owner | [MPSU](https://repo.masters-masters.com/en/owners/MPSU) |
| Stars | 362 |
| Forks | 89 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | CC-BY-SA-4.0 |
| Created | 2023 |
| Topics | fpga, riscv, systemverilog, risc-v, rv32i, study |
| Tier | [Alpha (250 to 699 ★)](https://repo.masters-masters.com/en/ranks/b_movie) |
| View on GitHub | [MPSU/APS](https://github.com/MPSU/APS) |

## Repository

Laboratory course on RISC-V Processor Development

The tier for repos with 250 to 699 ★. Published odds per card pulled: 20%. Rarity: Uncommon.

## More repos by MPSU

- [MPSU/exAPS · ★ 101 · Prototype](https://repo.masters-masters.com/en/repos/MPSU/exAPS)

## Nearby in SystemVerilog

- [chipsalliance/sv-tests · ★ 406 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/chipsalliance/sv-tests)
- [facebookresearch/deepfloat · ★ 401 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/facebookresearch/deepfloat)
- [pulp-platform/FlooNoC · ★ 371 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/pulp-platform/FlooNoC)
- [chipsalliance/Cores-VeeR-EL2 · ★ 349 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/chipsalliance/Cores-VeeR-EL2)
- [RHSResearchLLC/NiteFury-and-LiteFury · ★ 337 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/RHSResearchLLC/NiteFury-and-LiteFury)
- [pulp-platform/riscv-dbg · ★ 333 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/pulp-platform/riscv-dbg)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.