# MiSTer-devel/Minimig-AGA\_MiSTer

<https://repo.masters-masters.com/en/repos/MiSTer-devel/Minimig-AGA_MiSTer>

[Home](https://repo.masters-masters.com/en) › [MiSTer-devel](https://repo.masters-masters.com/en/owners/MiSTer-devel) › [Minimig-AGA\_MiSTer](https://repo.masters-masters.com/en/repos/MiSTer-devel/Minimig-AGA_MiSTer)

MiSTer-devel/Minimig-AGA\_MiSTer has 191 stars on GitHub. Its RepoMasters card: Prototype tier. Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [MiSTer-devel](https://repo.masters-masters.com/en/owners/MiSTer-devel) |
| Stars | 191 |
| Forks | 81 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | None |
| Created | 2017 |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [MiSTer-devel/Minimig-AGA\_MiSTer](https://github.com/MiSTer-devel/Minimig-AGA_MiSTer) |

## Repository

No description.

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by MiSTer-devel

- [MiSTer-devel/Main\_MiSTer · ★ 3,307 · C++ · RC](https://repo.masters-masters.com/en/repos/MiSTer-devel/Main_MiSTer)
- [MiSTer-devel/mr-fusion · ★ 391 · Shell · Alpha](https://repo.masters-masters.com/en/repos/MiSTer-devel/mr-fusion)
- [MiSTer-devel/ao486\_MiSTer · ★ 374 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/MiSTer-devel/ao486_MiSTer)
- [MiSTer-devel/Hardware\_MiSTer · ★ 300 · HTML · Alpha](https://repo.masters-masters.com/en/repos/MiSTer-devel/Hardware_MiSTer)
- [MiSTer-devel/PSX\_MiSTer · ★ 277 · VHDL · Alpha](https://repo.masters-masters.com/en/repos/MiSTer-devel/PSX_MiSTer)
- [MiSTer-devel/SNES\_MiSTer · ★ 247 · VHDL · Prototype](https://repo.masters-masters.com/en/repos/MiSTer-devel/SNES_MiSTer)

## Nearby in Verilog

- [FPGADude/Digital-Design · ★ 193 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/FPGADude/Digital-Design)
- [bluespec/Toooba · ★ 192 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/bluespec/Toooba)
- [ZFTurbo/MobileNet-in-FPGA · ★ 191 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/ZFTurbo/MobileNet-in-FPGA)
- [FPGAwars/FPGA-peripherals · ★ 189 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/FPGAwars/FPGA-peripherals)
- [mtmd/FPGA\_Based\_CNN · ★ 187 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/mtmd/FPGA_Based_CNN)
- [flytt-away/FPGA-Video-Capture · ★ 187 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/flytt-away/FPGA-Video-Capture)

---
Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.