# PrincetonUniversity/AutoSVA

<https://repo.masters-masters.com/en/repos/PrincetonUniversity/AutoSVA>

[Home](https://repo.masters-masters.com/en) › [PrincetonUniversity](https://repo.masters-masters.com/en/owners/PrincetonUniversity) › [AutoSVA](https://repo.masters-masters.com/en/repos/PrincetonUniversity/AutoSVA)

PrincetonUniversity/AutoSVA has 105 stars on GitHub. Its RepoMasters card: Prototype tier. AutoSVA is a tool to automatically generate formal testbenches for…

| Field | Value |
| --- | --- |
| Owner | [PrincetonUniversity](https://repo.masters-masters.com/en/owners/PrincetonUniversity) |
| Stars | 105 |
| Forks | 29 |
| Language | [Python](https://repo.masters-masters.com/en/languages/python) |
| License | None |
| Created | 2021 |
| Topics | design, verification, rtl, verilog, systemverilog, sva, methodology-development |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [PrincetonUniversity/AutoSVA](https://github.com/PrincetonUniversity/AutoSVA) |

## Repository

AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.
