# PyHDI/Pyverilog

<https://repo.masters-masters.com/en/repos/PyHDI/Pyverilog>

[Home](https://repo.masters-masters.com/en) › [PyHDI](https://repo.masters-masters.com/en/owners/PyHDI) › [Pyverilog](https://repo.masters-masters.com/en/repos/PyHDI/Pyverilog)

PyHDI/Pyverilog has 802 stars on GitHub. Its RepoMasters card: Beta tier. Python-based Hardware Design Processing Toolkit for Verilog HDL Language: Python.

| Field | Value |
| --- | --- |
| Owner | [PyHDI](https://repo.masters-masters.com/en/owners/PyHDI) |
| Stars | 802 |
| Forks | 213 |
| Language | [Python](https://repo.masters-masters.com/en/languages/python) |
| License | Apache-2.0 |
| Created | 2013 |
| Topics | verilog-hdl, hardware, compiler, parser, dataflow-analyzer, control-flow-analyzer, code-generator, python |
| Tier | [Beta (700 to 1,999 ★)](https://repo.masters-masters.com/en/ranks/box_office) |
| View on GitHub | [PyHDI/Pyverilog](https://github.com/PyHDI/Pyverilog) |

## Repository

Python-based Hardware Design Processing Toolkit for Verilog HDL

The tier for repos with 700 to 1,999 ★. Published odds per card pulled: 6%. Rarity: Rare.

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Data: GitHub · Illustration: the project’s public image, pixelated by RepoMasters.