# RISC-KC/basic\_rv32s

<https://repo.masters-masters.com/en/repos/RISC-KC/basic_rv32s>

[Home](https://repo.masters-masters.com/en) › [RISC-KC](https://repo.masters-masters.com/en/owners/RISC-KC) › [basic\_rv32s](https://repo.masters-masters.com/en/repos/RISC-KC/basic_rv32s)

RISC-KC/basic\_rv32s has 112 stars on GitHub. Its RepoMasters card: Prototype tier. 🎓 Instructional RISC-V processor design framework: single-cycle to 5-stage…

| Field | Value |
| --- | --- |
| Owner | [RISC-KC](https://repo.masters-masters.com/en/owners/RISC-KC) |
| Stars | 112 |
| Forks | 11 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | MIT |
| Created | 2024 |
| Topics | computer-architecture, computer-science, cpu, dhrystone, fpga, hdl, processor, processor-design, risc-v, riscv |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [RISC-KC/basic\_rv32s](https://github.com/RISC-KC/basic_rv32s) |

## Repository

🎓 Instructional RISC-V processor design framework: single-cycle to 5-stage pipeline with FPGA verification and complete learning guidelines\! A RISC-V CPU design guideline.

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.