# RoaLogic/RV12

<https://repo.masters-masters.com/en/repos/RoaLogic/RV12>

[Home](https://repo.masters-masters.com/en) › [RoaLogic](https://repo.masters-masters.com/en/owners/RoaLogic) › [RV12](https://repo.masters-masters.com/en/repos/RoaLogic/RV12)

RoaLogic/RV12 has 454 stars on GitHub. Its RepoMasters card: Alpha tier. RISC-V CPU Core Language: SystemVerilog.

| Field | Value |
| --- | --- |
| Owner | [RoaLogic](https://repo.masters-masters.com/en/owners/RoaLogic) |
| Stars | 454 |
| Forks | 61 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | None |
| Created | 2017 |
| Topics | risc-v, 32-bit, 64bit, cpu |
| Tier | [Alpha (250 to 699 ★)](https://repo.masters-masters.com/en/ranks/b_movie) |
| View on GitHub | [RoaLogic/RV12](https://github.com/RoaLogic/RV12) |

## Repository

RISC-V CPU Core

The tier for repos with 250 to 699 ★. Published odds per card pulled: 20%. Rarity: Uncommon.

## More repos by RoaLogic

- [RoaLogic/ahb3lite\_interconnect · ★ 110 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/RoaLogic/ahb3lite_interconnect)

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- [WangXuan95/USTC-RVSoC · ★ 442 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/WangXuan95/USTC-RVSoC)
- [raulbehl/100DaysOfRTL · ★ 429 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/raulbehl/100DaysOfRTL)
- [gtaylormb/opl3\_fpga · ★ 410 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/gtaylormb/opl3_fpga)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.