# RongyeL/EasyAXI

<https://repo.masters-masters.com/en/repos/RongyeL/EasyAXI>

[Home](https://repo.masters-masters.com/en) › [RongyeL](https://repo.masters-masters.com/en/owners/RongyeL) › [EasyAXI](https://repo.masters-masters.com/en/repos/RongyeL/EasyAXI)

RongyeL/EasyAXI has 141 stars on GitHub. Its RepoMasters card: Prototype tier. Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [RongyeL](https://repo.masters-masters.com/en/owners/RongyeL) |
| Stars | 141 |
| Forks | 16 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | Apache-2.0 |
| Created | 2025 |
| Topics | verilog |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [RongyeL/EasyAXI](https://github.com/RongyeL/EasyAXI) |

## Repository

No description.

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## Nearby in Verilog

- [MoonshotAI/nano-kpu · ★ 144 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/MoonshotAI/nano-kpu)
- [abdelazeem201/Cadence-RTL-to-GDSII-Flow · ★ 141 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/abdelazeem201/Cadence-RTL-to-GDSII-Flow)
- [Azalea8/riscv\_cpu · ★ 141 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/Azalea8/riscv_cpu)
- [MiSTer-devel/Gameboy\_MiSTer · ★ 140 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/MiSTer-devel/Gameboy_MiSTer)
- [WangXuan95/FPGA-SDfake · ★ 140 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-SDfake)

---
Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.