# SparcLab/OpenSERDES

<https://repo.masters-masters.com/en/repos/SparcLab/OpenSERDES>

[Home](https://repo.masters-masters.com/en) › [SparcLab](https://repo.masters-masters.com/en/owners/SparcLab) › [OpenSERDES](https://repo.masters-masters.com/en/repos/SparcLab/OpenSERDES)

SparcLab/OpenSERDES has 309 stars on GitHub. Its RepoMasters card: Alpha tier. Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm…

| Field | Value |
| --- | --- |
| Owner | [SparcLab](https://repo.masters-masters.com/en/owners/SparcLab) |
| Stars | 309 |
| Forks | 53 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | GPL-3.0 |
| Created | 2020 |
| Topics | digitalarchitecture, serdes, openlane, skywater, openpdk |
| Tier | [Alpha (250 to 699 ★)](https://repo.masters-masters.com/en/ranks/b_movie) |
| View on GitHub | [SparcLab/OpenSERDES](https://github.com/SparcLab/OpenSERDES) |

## Repository

Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.

The tier for repos with 250 to 699 ★. Published odds per card pulled: 20%. Rarity: Uncommon.

## Nearby in Verilog

- [Xilinx/libsystemctlm-soc · ★ 312 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/Xilinx/libsystemctlm-soc)
- [Modos-Labs/Caster · ★ 312 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/Modos-Labs/Caster)
- [fromgof/TridentVision · ★ 312 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/fromgof/TridentVision)
- [budude2/openfpga-GBC · ★ 308 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/budude2/openfpga-GBC)
- [damdoy/ice40\_ultraplus\_examples · ★ 302 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/damdoy/ice40_ultraplus_examples)
- [efabless/raven-picorv32 · ★ 299 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/efabless/raven-picorv32)

---
Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.