# SpinalHDL/VexRiscv

<https://repo.masters-masters.com/en/repos/SpinalHDL/VexRiscv>

[Home](https://repo.masters-masters.com/en) › [SpinalHDL](https://repo.masters-masters.com/en/owners/SpinalHDL) › [VexRiscv](https://repo.masters-masters.com/en/repos/SpinalHDL/VexRiscv)

SpinalHDL/VexRiscv has 3,302 stars on GitHub. Its RepoMasters card: RC tier. A FPGA friendly 32 bit RISC-V CPU implementation Language: Assembly.

| Field | Value |
| --- | --- |
| Owner | [SpinalHDL](https://repo.masters-masters.com/en/owners/SpinalHDL) |
| Stars | 3,302 |
| Forks | 519 |
| Language | [Assembly](https://repo.masters-masters.com/en/languages/assembly) |
| License | MIT |
| Created | 2017 |
| Topics | riscv, soc, cpu, spinalhdl, vhdl, verilog, fpga, softcore |
| Tier | [RC (2,000 to 4,999 ★)](https://repo.masters-masters.com/en/ranks/blockbuster) |
| View on GitHub | [SpinalHDL/VexRiscv](https://github.com/SpinalHDL/VexRiscv) |

## Repository

A FPGA friendly 32 bit RISC-V CPU implementation

The tier for repos with 2,000 to 4,999 ★. Published odds per card pulled: 3%. Rarity: Epic.

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Data: GitHub · Illustration: the project’s public image, pixelated by RepoMasters.