# SymbioticEDA/riscv-formal

<https://repo.masters-masters.com/en/repos/SymbioticEDA/riscv-formal>

[Home](https://repo.masters-masters.com/en) › [SymbioticEDA](https://repo.masters-masters.com/en/owners/SymbioticEDA) › [riscv-formal](https://repo.masters-masters.com/en/repos/SymbioticEDA/riscv-formal)

SymbioticEDA/riscv-formal has 634 stars on GitHub. Its RepoMasters card: Alpha tier. RISC-V Formal Verification Framework Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [SymbioticEDA](https://repo.masters-masters.com/en/owners/SymbioticEDA) |
| Stars | 634 |
| Forks | 106 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | ISC |
| Created | 2016 |
| Tier | [Alpha (250 to 699 ★)](https://repo.masters-masters.com/en/ranks/b_movie) |
| View on GitHub | [SymbioticEDA/riscv-formal](https://github.com/SymbioticEDA/riscv-formal) |

## Repository

RISC-V Formal Verification Framework

The tier for repos with 250 to 699 ★. Published odds per card pulled: 20%. Rarity: Uncommon.

## Nearby in Verilog

- [ultraembedded/core\_ddr3\_controller · ★ 646 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/ultraembedded/core_ddr3_controller)
- [dtysky/FPGA-Imaging-Library · ★ 644 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/dtysky/FPGA-Imaging-Library)
- [The-OpenROAD-Project/OpenSTA · ★ 639 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/The-OpenROAD-Project/OpenSTA)
- [seldridge/verilog · ★ 632 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/seldridge/verilog)
- [danielholanda/LeFlow · ★ 630 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/danielholanda/LeFlow)
- [omarelhedaby/CNN-FPGA · ★ 614 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/omarelhedaby/CNN-FPGA)

---
Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.