# TerosTechnology/vscode-terosHDL

<https://repo.masters-masters.com/en/repos/TerosTechnology/vscode-terosHDL>

[Home](https://repo.masters-masters.com/en) › [TerosTechnology](https://repo.masters-masters.com/en/owners/TerosTechnology) › [vscode-terosHDL](https://repo.masters-masters.com/en/repos/TerosTechnology/vscode-terosHDL)

TerosTechnology/vscode-terosHDL has 745 stars on GitHub. Its RepoMasters card: Beta tier. VHDL and Verilog/SV IDE: state machine viewer, linter… Language: VHDL.

| Field | Value |
| --- | --- |
| Owner | [TerosTechnology](https://repo.masters-masters.com/en/owners/TerosTechnology) |
| Stars | 745 |
| Forks | 78 |
| Language | [VHDL](https://repo.masters-masters.com/en/languages/vhdl) |
| License | GPL-3.0 |
| Created | 2020 |
| Topics | verilog, vhdl, systemverilog, fpga |
| Tier | [Beta (700 to 1,999 ★)](https://repo.masters-masters.com/en/ranks/box_office) |
| View on GitHub | [TerosTechnology/vscode-terosHDL](https://github.com/TerosTechnology/vscode-terosHDL) |

## Repository

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more\!

The tier for repos with 700 to 1,999 ★. Published odds per card pulled: 6%. Rarity: Rare.

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Data: GitHub · Illustration: the project’s public image, pixelated by RepoMasters.