# TimRudy/ice-chips-verilog

<https://repo.masters-masters.com/en/repos/TimRudy/ice-chips-verilog>

[Home](https://repo.masters-masters.com/en) › [TimRudy](https://repo.masters-masters.com/en/owners/TimRudy) › [ice-chips-verilog](https://repo.masters-masters.com/en/repos/TimRudy/ice-chips-verilog)

TimRudy/ice-chips-verilog has 160 stars on GitHub. Its RepoMasters card: Prototype tier. IceChips is a library of all common discrete logic devices in Verilog

| Field | Value |
| --- | --- |
| Owner | [TimRudy](https://repo.masters-masters.com/en/owners/TimRudy) |
| Stars | 160 |
| Forks | 26 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | GPL-3.0 |
| Created | 2017 |
| Topics | 7400, verilog-components, eda, logic-circuit, fpga, iverilog, open-hardware, digital-logic, icestorm |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [TimRudy/ice-chips-verilog](https://github.com/TimRudy/ice-chips-verilog) |

## Repository

IceChips is a library of all common discrete logic devices in Verilog

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## Nearby in Verilog

- [zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial · ★ 160 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial)
- [KASIRGA-KIZIL/tekno-kizil · ★ 160 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/KASIRGA-KIZIL/tekno-kizil)
- [Kyrie-T/HPMM · ★ 160 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/Kyrie-T/HPMM)
- [MasLiang/CNN-On-FPGA · ★ 159 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/MasLiang/CNN-On-FPGA)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.