# Verdvana/AXI4\_Interconnect

<https://repo.masters-masters.com/en/repos/Verdvana/AXI4_Interconnect>

[Home](https://repo.masters-masters.com/en) › [Verdvana](https://repo.masters-masters.com/en/owners/Verdvana) › [AXI4\_Interconnect](https://repo.masters-masters.com/en/repos/Verdvana/AXI4_Interconnect)

Verdvana/AXI4\_Interconnect has 111 stars on GitHub. Its RepoMasters card: Prototype tier. AXI总线连接器 Language: SystemVerilog.

| Field | Value |
| --- | --- |
| Owner | [Verdvana](https://repo.masters-masters.com/en/owners/Verdvana) |
| Stars | 111 |
| Forks | 24 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | None |
| Created | 2020 |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [Verdvana/AXI4\_Interconnect](https://github.com/Verdvana/AXI4_Interconnect) |

## Repository

AXI总线连接器

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.