# WangXuan95/FPGA-FixedPoint

<https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-FixedPoint>

[Home](https://repo.masters-masters.com/en) › [WangXuan95](https://repo.masters-masters.com/en/owners/WangXuan95) › [FPGA-FixedPoint](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-FixedPoint)

WangXuan95/FPGA-FixedPoint has 241 stars on GitHub. Its RepoMasters card: Prototype tier. Verilog implementation of fixed-point numbers, supports custom bit…

| Field | Value |
| --- | --- |
| Owner | [WangXuan95](https://repo.masters-masters.com/en/owners/WangXuan95) |
| Stars | 241 |
| Forks | 42 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | GPL-3.0 |
| Created | 2019 |
| Topics | verilog, rtl, systemverilog, fixedpoint, arithmetic, pipeline |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [WangXuan95/FPGA-FixedPoint](https://github.com/WangXuan95/FPGA-FixedPoint) |

## Repository

Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by WangXuan95

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- [WangXuan95/Xilinx-FPGA-PCIe-XDMA-Tutorial · ★ 869 · Batchfile · Beta](https://repo.masters-masters.com/en/repos/WangXuan95/Xilinx-FPGA-PCIe-XDMA-Tutorial)
- [WangXuan95/BSV\_Tutorial\_cn · ★ 612 · Bluespec · Alpha](https://repo.masters-masters.com/en/repos/WangXuan95/BSV_Tutorial_cn)
- [WangXuan95/USTC-RVSoC · ★ 442 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/WangXuan95/USTC-RVSoC)
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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.