# WangXuan95/FPGA-HDMI

<https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-HDMI>

[Home](https://repo.masters-masters.com/en) › [WangXuan95](https://repo.masters-masters.com/en/owners/WangXuan95) › [FPGA-HDMI](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-HDMI)

WangXuan95/FPGA-HDMI has 119 stars on GitHub. Its RepoMasters card: Prototype tier. An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器 Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [WangXuan95](https://repo.masters-masters.com/en/owners/WangXuan95) |
| Stars | 119 |
| Forks | 22 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | GPL-3.0 |
| Created | 2024 |
| Topics | fpga, hdmi, rtl, systemverilog, verilog, video, video-display, hdmi-tx |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [WangXuan95/FPGA-HDMI](https://github.com/WangXuan95/FPGA-HDMI) |

## Repository

An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by WangXuan95

- [WangXuan95/FPGA-FOC · ★ 994 · Verilog · Beta](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-FOC)
- [WangXuan95/FPGA-USB-Device · ★ 934 · Verilog · Beta](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-USB-Device)
- [WangXuan95/Xilinx-FPGA-PCIe-XDMA-Tutorial · ★ 869 · Batchfile · Beta](https://repo.masters-masters.com/en/repos/WangXuan95/Xilinx-FPGA-PCIe-XDMA-Tutorial)
- [WangXuan95/BSV\_Tutorial\_cn · ★ 612 · Bluespec · Alpha](https://repo.masters-masters.com/en/repos/WangXuan95/BSV_Tutorial_cn)
- [WangXuan95/USTC-RVSoC · ★ 442 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/WangXuan95/USTC-RVSoC)
- [WangXuan95/FPGA-ftdi245fifo · ★ 363 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-ftdi245fifo)

## Nearby in Verilog

- [gt-synergy-lab/SIGMA · ★ 119 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/gt-synergy-lab/SIGMA)
- [spacemen3/PDP-1 · ★ 119 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/spacemen3/PDP-1)
- [Ummidichandrika/100-Days-of-RTL · ★ 119 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/Ummidichandrika/100-Days-of-RTL)
- [freecores/8051 · ★ 118 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/freecores/8051)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.