# WangXuan95/FPGA-SATA-HBA

<https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-SATA-HBA>

[Home](https://repo.masters-masters.com/en) › [WangXuan95](https://repo.masters-masters.com/en/owners/WangXuan95) › [FPGA-SATA-HBA](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-SATA-HBA)

WangXuan95/FPGA-SATA-HBA has 148 stars on GitHub. Its RepoMasters card: Prototype tier. A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write…

| Field | Value |
| --- | --- |
| Owner | [WangXuan95](https://repo.masters-masters.com/en/owners/WangXuan95) |
| Stars | 148 |
| Forks | 47 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | GPL-3.0 |
| Created | 2022 |
| Topics | fpga, sata, sata-controller, systemverilog, verilog, sata-core, sata-hba, sata-hba-controller, sata-hba-core, virtex-7 |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [WangXuan95/FPGA-SATA-HBA](https://github.com/WangXuan95/FPGA-SATA-HBA) |

## Repository

A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器，用来读写硬盘。

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by WangXuan95

- [WangXuan95/FPGA-FOC · ★ 994 · Verilog · Beta](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-FOC)
- [WangXuan95/FPGA-USB-Device · ★ 934 · Verilog · Beta](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-USB-Device)
- [WangXuan95/Xilinx-FPGA-PCIe-XDMA-Tutorial · ★ 869 · Batchfile · Beta](https://repo.masters-masters.com/en/repos/WangXuan95/Xilinx-FPGA-PCIe-XDMA-Tutorial)
- [WangXuan95/BSV\_Tutorial\_cn · ★ 612 · Bluespec · Alpha](https://repo.masters-masters.com/en/repos/WangXuan95/BSV_Tutorial_cn)
- [WangXuan95/USTC-RVSoC · ★ 442 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/WangXuan95/USTC-RVSoC)
- [WangXuan95/FPGA-ftdi245fifo · ★ 363 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-ftdi245fifo)

## Nearby in SystemVerilog

- [Dollbar/Overflow · ★ 153 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/Dollbar/Overflow)
- [waviousllc/wav-lpddr-hw · ★ 148 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/waviousllc/wav-lpddr-hw)
- [amd/mini-isp · ★ 148 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/amd/mini-isp)
- [ic-lab-duth/RISC-V-Vector · ★ 147 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/ic-lab-duth/RISC-V-Vector)
- [zeroasiccorp/wildebeest · ★ 146 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/zeroasiccorp/wildebeest)

---
Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.