# WangXuan95/FPGA-SDfake

<https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-SDfake>

[Home](https://repo.masters-masters.com/en) › [WangXuan95](https://repo.masters-masters.com/en/owners/WangXuan95) › [FPGA-SDfake](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-SDfake)

WangXuan95/FPGA-SDfake has 140 stars on GitHub. Its RepoMasters card: Prototype tier. Imitate SDcard using FPGAs. 使用FPGA模拟伪装SD卡。 Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [WangXuan95](https://repo.masters-masters.com/en/owners/WangXuan95) |
| Stars | 140 |
| Forks | 29 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | GPL-3.0 |
| Created | 2019 |
| Topics | rtl, sdcard, verilog, systemverilog, fpga, sdio |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [WangXuan95/FPGA-SDfake](https://github.com/WangXuan95/FPGA-SDfake) |

## Repository

Imitate SDcard using FPGAs. 使用FPGA模拟伪装SD卡。

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by WangXuan95

- [WangXuan95/FPGA-FOC · ★ 994 · Verilog · Beta](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-FOC)
- [WangXuan95/FPGA-USB-Device · ★ 934 · Verilog · Beta](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-USB-Device)
- [WangXuan95/Xilinx-FPGA-PCIe-XDMA-Tutorial · ★ 869 · Batchfile · Beta](https://repo.masters-masters.com/en/repos/WangXuan95/Xilinx-FPGA-PCIe-XDMA-Tutorial)
- [WangXuan95/BSV\_Tutorial\_cn · ★ 612 · Bluespec · Alpha](https://repo.masters-masters.com/en/repos/WangXuan95/BSV_Tutorial_cn)
- [WangXuan95/USTC-RVSoC · ★ 442 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/WangXuan95/USTC-RVSoC)
- [WangXuan95/FPGA-ftdi245fifo · ★ 363 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-ftdi245fifo)

## Nearby in Verilog

- [RongyeL/EasyAXI · ★ 141 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/RongyeL/EasyAXI)
- [MiSTer-devel/Gameboy\_MiSTer · ★ 140 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/MiSTer-devel/Gameboy_MiSTer)
- [HDLForBeginners/Examples · ★ 140 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/HDLForBeginners/Examples)
- [russdill/bch\_verilog · ★ 139 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/russdill/bch_verilog)
- [AngeloJacobo/RISC-V · ★ 139 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/AngeloJacobo/RISC-V)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.