# WangXuan95/FPGA-UART

<https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-UART>

[Home](https://repo.masters-masters.com/en) › [WangXuan95](https://repo.masters-masters.com/en/owners/WangXuan95) › [FPGA-UART](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-UART)

WangXuan95/FPGA-UART has 354 stars on GitHub. Its RepoMasters card: Alpha tier. This repo includes 3 independent modules: UART receiver, UART transmitter…

| Field | Value |
| --- | --- |
| Owner | [WangXuan95](https://repo.masters-masters.com/en/owners/WangXuan95) |
| Stars | 354 |
| Forks | 55 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | GPL-3.0 |
| Created | 2019 |
| Topics | uart, verilog, rtl, fpga |
| Tier | [Alpha (250 to 699 ★)](https://repo.masters-masters.com/en/ranks/b_movie) |
| View on GitHub | [WangXuan95/FPGA-UART](https://github.com/WangXuan95/FPGA-UART) |

## Repository

This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。

The tier for repos with 250 to 699 ★. Published odds per card pulled: 20%. Rarity: Uncommon.

## More repos by WangXuan95

- [WangXuan95/FPGA-FOC · ★ 994 · Verilog · Beta](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-FOC)
- [WangXuan95/FPGA-USB-Device · ★ 934 · Verilog · Beta](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-USB-Device)
- [WangXuan95/Xilinx-FPGA-PCIe-XDMA-Tutorial · ★ 869 · Batchfile · Beta](https://repo.masters-masters.com/en/repos/WangXuan95/Xilinx-FPGA-PCIe-XDMA-Tutorial)
- [WangXuan95/BSV\_Tutorial\_cn · ★ 612 · Bluespec · Alpha](https://repo.masters-masters.com/en/repos/WangXuan95/BSV_Tutorial_cn)
- [WangXuan95/USTC-RVSoC · ★ 442 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/WangXuan95/USTC-RVSoC)
- [WangXuan95/FPGA-ftdi245fifo · ★ 363 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-ftdi245fifo)

## Nearby in Verilog

- [16SalomonArs/Pcileech-DMA-NVMe-VMD · ★ 358 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/16SalomonArs/Pcileech-DMA-NVMe-VMD)
- [FPGAwars/icezum · ★ 357 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/FPGAwars/icezum)
- [ZipCPU/wbuart32 · ★ 356 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/ZipCPU/wbuart32)
- [WangXuan95/FPGA-SDcard-Reader · ★ 351 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-SDcard-Reader)
- [WangXuan95/FPGA-JPEG-LS-encoder · ★ 347 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-JPEG-LS-encoder)
- [marmolejo/zet · ★ 345 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/marmolejo/zet)

---
Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.