# WangXuan95/FPGA-ftdi245fifo

<https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-ftdi245fifo>

[Home](https://repo.masters-masters.com/en) › [WangXuan95](https://repo.masters-masters.com/en/owners/WangXuan95) › [FPGA-ftdi245fifo](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-ftdi245fifo)

WangXuan95/FPGA-ftdi245fifo has 363 stars on GitHub. Its RepoMasters card: Alpha tier. An FPGA-based FT232H/FT600 chip controller for rapid data transmission…

| Field | Value |
| --- | --- |
| Owner | [WangXuan95](https://repo.masters-masters.com/en/owners/WangXuan95) |
| Stars | 363 |
| Forks | 97 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | GPL-3.0 |
| Created | 2019 |
| Topics | usb, ft232h, ft600, ft601, fpga, systemverilog, ipcore, verilog, rtl |
| Tier | [Alpha (250 to 699 ★)](https://repo.masters-masters.com/en/ranks/b_movie) |
| View on GitHub | [WangXuan95/FPGA-ftdi245fifo](https://github.com/WangXuan95/FPGA-ftdi245fifo) |

## Repository

An FPGA-based FT232H/FT600 chip controller for rapid data transmission via USB. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。

The tier for repos with 250 to 699 ★. Published odds per card pulled: 20%. Rarity: Uncommon.

## More repos by WangXuan95

- [WangXuan95/FPGA-FOC · ★ 994 · Verilog · Beta](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-FOC)
- [WangXuan95/FPGA-USB-Device · ★ 934 · Verilog · Beta](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-USB-Device)
- [WangXuan95/Xilinx-FPGA-PCIe-XDMA-Tutorial · ★ 869 · Batchfile · Beta](https://repo.masters-masters.com/en/repos/WangXuan95/Xilinx-FPGA-PCIe-XDMA-Tutorial)
- [WangXuan95/BSV\_Tutorial\_cn · ★ 612 · Bluespec · Alpha](https://repo.masters-masters.com/en/repos/WangXuan95/BSV_Tutorial_cn)
- [WangXuan95/USTC-RVSoC · ★ 442 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/WangXuan95/USTC-RVSoC)
- [WangXuan95/FPGA-CAN · ★ 363 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-CAN)

## Nearby in Verilog

- [MiSTer-devel/ao486\_MiSTer · ★ 374 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/MiSTer-devel/ao486_MiSTer)
- [wuxx/Colorlight-FPGA-Projects · ★ 372 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/wuxx/Colorlight-FPGA-Projects)
- [WangXuan95/FPGA-CAN · ★ 363 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-CAN)
- [TILOS-AI-Institute/MacroPlacement · ★ 358 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/TILOS-AI-Institute/MacroPlacement)
- [16SalomonArs/Pcileech-DMA-NVMe-VMD · ★ 358 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/16SalomonArs/Pcileech-DMA-NVMe-VMD)
- [FPGAwars/icezum · ★ 357 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/FPGAwars/icezum)

---
Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.
