# WangXuan95/USTC-RVSoC

<https://repo.masters-masters.com/en/repos/WangXuan95/USTC-RVSoC>

[Home](https://repo.masters-masters.com/en) › [WangXuan95](https://repo.masters-masters.com/en/owners/WangXuan95) › [USTC-RVSoC](https://repo.masters-masters.com/en/repos/WangXuan95/USTC-RVSoC)

WangXuan95/USTC-RVSoC has 442 stars on GitHub. Its RepoMasters card: Alpha tier. An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus…

| Field | Value |
| --- | --- |
| Owner | [WangXuan95](https://repo.masters-masters.com/en/owners/WangXuan95) |
| Stars | 442 |
| Forks | 81 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | GPL-3.0 |
| Created | 2019 |
| Topics | riscv, risc-v, rv32i, soc, fpga, softcore, rtl, verilog, systemverilog, cpu |
| Tier | [Alpha (250 to 699 ★)](https://repo.masters-masters.com/en/ranks/b_movie) |
| View on GitHub | [WangXuan95/USTC-RVSoC](https://github.com/WangXuan95/USTC-RVSoC) |

## Repository

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

The tier for repos with 250 to 699 ★. Published odds per card pulled: 20%. Rarity: Uncommon.

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## Nearby in SystemVerilog

- [VerificationExcellence/SystemVerilogReference · ★ 473 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/VerificationExcellence/SystemVerilogReference)
- [fpgasystems/Coyote · ★ 469 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/fpgasystems/Coyote)
- [RoaLogic/RV12 · ★ 454 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/RoaLogic/RV12)
- [raulbehl/100DaysOfRTL · ★ 428 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/raulbehl/100DaysOfRTL)
- [gtaylormb/opl3\_fpga · ★ 410 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/gtaylormb/opl3_fpga)
- [chipsalliance/sv-tests · ★ 406 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/chipsalliance/sv-tests)

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