# WilsonChen003/HDLGen

<https://repo.masters-masters.com/en/repos/WilsonChen003/HDLGen>

[Home](https://repo.masters-masters.com/en) › [WilsonChen003](https://repo.masters-masters.com/en/owners/WilsonChen003) › [HDLGen](https://repo.masters-masters.com/en/repos/WilsonChen003/HDLGen)

WilsonChen003/HDLGen has 115 stars on GitHub. Its RepoMasters card: Prototype tier. HDLGen is an HDL generation tool, supporting embedded Perl or Python…

| Field | Value |
| --- | --- |
| Owner | [WilsonChen003](https://repo.masters-masters.com/en/owners/WilsonChen003) |
| Stars | 115 |
| Forks | 30 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | None |
| Created | 2022 |
| Topics | automation, hdl, perl, python, script, verilog, asic, soc, rtl |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [WilsonChen003/HDLGen](https://github.com/WilsonChen003/HDLGen) |

## Repository

HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## Nearby in Verilog

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- [Misaka-N/TJCS-SingleCircleCPU31 · ★ 115 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/Misaka-N/TJCS-SingleCircleCPU31)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.