# XUANTIE-RV/openc910

<https://repo.masters-masters.com/en/repos/XUANTIE-RV/openc910>

[Home](https://repo.masters-masters.com/en) › [XUANTIE-RV](https://repo.masters-masters.com/en/owners/XUANTIE-RV) › [openc910](https://repo.masters-masters.com/en/repos/XUANTIE-RV/openc910)

XUANTIE-RV/openc910 has 1,490 stars on GitHub. Its RepoMasters card: Beta tier. OpenXuantie - OpenC910 Core Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [XUANTIE-RV](https://repo.masters-masters.com/en/owners/XUANTIE-RV) |
| Stars | 1,490 |
| Forks | 406 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | Apache-2.0 |
| Created | 2021 |
| Tier | [Beta (700 to 1,999 ★)](https://repo.masters-masters.com/en/ranks/box_office) |
| View on GitHub | [XUANTIE-RV/openc910](https://github.com/XUANTIE-RV/openc910) |

## Repository

OpenXuantie - OpenC910 Core

The tier for repos with 700 to 1,999 ★. Published odds per card pulled: 6%. Rarity: Rare.

## More repos by XUANTIE-RV

- [XUANTIE-RV/wujian100\_open · ★ 2,031 · Verilog · RC](https://repo.masters-masters.com/en/repos/XUANTIE-RV/wujian100_open)
- [XUANTIE-RV/riscv-aosp · ★ 483 · Alpha](https://repo.masters-masters.com/en/repos/XUANTIE-RV/riscv-aosp)
- [XUANTIE-RV/openc906 · ★ 425 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/XUANTIE-RV/openc906)
- [XUANTIE-RV/riscv-matrix-extension-spec · ★ 190 · Makefile · Prototype](https://repo.masters-masters.com/en/repos/XUANTIE-RV/riscv-matrix-extension-spec)
- [XUANTIE-RV/opene902 · ★ 180 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/XUANTIE-RV/opene902)
- [XUANTIE-RV/opene906 · ★ 180 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/XUANTIE-RV/opene906)

## Nearby in Verilog

- [ultraembedded/riscv · ★ 1,811 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ultraembedded/riscv)
- [alexforencich/verilog-pcie · ★ 1,675 · Verilog · Beta](https://repo.masters-masters.com/en/repos/alexforencich/verilog-pcie)
- [ZipCPU/zipcpu · ★ 1,597 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ZipCPU/zipcpu)
- [aolofsson/oh · ★ 1,440 · Verilog · Beta](https://repo.masters-masters.com/en/repos/aolofsson/oh)
- [VerticalResearchGroup/miaow · ★ 1,430 · Verilog · Beta](https://repo.masters-masters.com/en/repos/VerticalResearchGroup/miaow)
- [tiny-tpu-v2/tiny-tpu · ★ 1,411 · Verilog · Beta](https://repo.masters-masters.com/en/repos/tiny-tpu-v2/tiny-tpu)

---
Data: GitHub · Illustration: the project’s public image, pixelated by RepoMasters.