# ZipCPU/dpll

<https://repo.masters-masters.com/en/repos/ZipCPU/dpll>

[Home](https://repo.masters-masters.com/en) › [ZipCPU](https://repo.masters-masters.com/en/owners/ZipCPU) › [dpll](https://repo.masters-masters.com/en/repos/ZipCPU/dpll)

ZipCPU/dpll has 123 stars on GitHub. Its RepoMasters card: Prototype tier. A collection of phase locked loop (PLL) related projects Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [ZipCPU](https://repo.masters-masters.com/en/owners/ZipCPU) |
| Stars | 123 |
| Forks | 30 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | None |
| Created | 2017 |
| Topics | verilog, pll, verilator, fpga, gplv3 |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [ZipCPU/dpll](https://github.com/ZipCPU/dpll) |

## Repository

A collection of phase locked loop (PLL) related projects

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.