# ZipCPU/openarty

<https://repo.masters-masters.com/en/repos/ZipCPU/openarty>

[Home](https://repo.masters-masters.com/en) › [ZipCPU](https://repo.masters-masters.com/en/owners/ZipCPU) › [openarty](https://repo.masters-masters.com/en/repos/ZipCPU/openarty)

ZipCPU/openarty has 133 stars on GitHub. Its RepoMasters card: Prototype tier. An Open Source configuration of the Arty platform Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [ZipCPU](https://repo.masters-masters.com/en/owners/ZipCPU) |
| Stars | 133 |
| Forks | 24 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | None |
| Created | 2016 |
| Topics | zipcpu, fpga, fpga-soc, arty, verilator, wishbone-bus, wishbone |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [ZipCPU/openarty](https://github.com/ZipCPU/openarty) |

## Repository

An Open Source configuration of the Arty platform

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by ZipCPU

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## Nearby in Verilog

- [Daniel-GGB/My-Digital-IC-Library · ★ 134 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/Daniel-GGB/My-Digital-IC-Library)
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- [robinhedwards/UltimateCart · ★ 133 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/robinhedwards/UltimateCart)
- [MiSTer-devel/Genesis\_MiSTer · ★ 132 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/MiSTer-devel/Genesis_MiSTer)
- [circuitgraph/circuitgraph · ★ 132 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/circuitgraph/circuitgraph)
- [phoeniX-Digital-Design/phoeniX · ★ 132 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/phoeniX-Digital-Design/phoeniX)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.