# ZipCPU/vgasim

<https://repo.masters-masters.com/en/repos/ZipCPU/vgasim>

[Home](https://repo.masters-masters.com/en) › [ZipCPU](https://repo.masters-masters.com/en/owners/ZipCPU) › [vgasim](https://repo.masters-masters.com/en/repos/ZipCPU/vgasim)

ZipCPU/vgasim has 185 stars on GitHub. Its RepoMasters card: Prototype tier. A Video display simulator Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [ZipCPU](https://repo.masters-masters.com/en/owners/ZipCPU) |
| Stars | 185 |
| Forks | 25 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | None |
| Created | 2017 |
| Topics | verilog, video, gplv3, fpga, gtkmm, video-simulator, verilator, vga |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [ZipCPU/vgasim](https://github.com/ZipCPU/vgasim) |

## Repository

A Video display simulator

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by ZipCPU

- [ZipCPU/zipcpu · ★ 1,597 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ZipCPU/zipcpu)
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- [ZipCPU/sdspi · ★ 425 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/ZipCPU/sdspi)
- [ZipCPU/wbuart32 · ★ 356 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/ZipCPU/wbuart32)
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- [ZipCPU/dblclockfft · ★ 269 · C++ · Alpha](https://repo.masters-masters.com/en/repos/ZipCPU/dblclockfft)

## Nearby in Verilog

- [flytt-away/FPGA-Video-Capture · ★ 187 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/flytt-away/FPGA-Video-Capture)
- [zhemao/ez8 · ★ 186 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/zhemao/ez8)
- [thousrm/universal\_NPU-CNN\_accelerator · ★ 185 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/thousrm/universal_NPU-CNN_accelerator)
- [openrisc/or1200 · ★ 184 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/openrisc/or1200)
- [pnnl/OpenCGRA · ★ 184 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/pnnl/OpenCGRA)
- [ash-olakangal/RISC-V-Processor · ★ 184 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/ash-olakangal/RISC-V-Processor)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.
