# ZipCPU/wb2axip

<https://repo.masters-masters.com/en/repos/ZipCPU/wb2axip>

[Home](https://repo.masters-masters.com/en) › [ZipCPU](https://repo.masters-masters.com/en/owners/ZipCPU) › [wb2axip](https://repo.masters-masters.com/en/repos/ZipCPU/wb2axip)

ZipCPU/wb2axip has 714 stars on GitHub. Its RepoMasters card: Beta tier. Bus bridges and other odds and ends Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [ZipCPU](https://repo.masters-masters.com/en/owners/ZipCPU) |
| Stars | 714 |
| Forks | 128 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | None |
| Created | 2016 |
| Topics | fpga, wishbone, wishbone-bus, axi-bus, xilinx, xilinx-vivado, gplv3 |
| Tier | [Beta (700 to 1,999 ★)](https://repo.masters-masters.com/en/ranks/box_office) |
| View on GitHub | [ZipCPU/wb2axip](https://github.com/ZipCPU/wb2axip) |

## Repository

Bus bridges and other odds and ends

The tier for repos with 700 to 1,999 ★. Published odds per card pulled: 6%. Rarity: Rare.

## More repos by ZipCPU

- [ZipCPU/zipcpu · ★ 1,597 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ZipCPU/zipcpu)
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- [ZipCPU/autofpga · ★ 194 · C++ · Prototype](https://repo.masters-masters.com/en/repos/ZipCPU/autofpga)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.