# ZipCPU/wbuart32

<https://repo.masters-masters.com/en/repos/ZipCPU/wbuart32>

[Home](https://repo.masters-masters.com/en) › [ZipCPU](https://repo.masters-masters.com/en/owners/ZipCPU) › [wbuart32](https://repo.masters-masters.com/en/repos/ZipCPU/wbuart32)

ZipCPU/wbuart32 has 356 stars on GitHub. Its RepoMasters card: Alpha tier. A simple, basic, formally verified UART controller Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [ZipCPU](https://repo.masters-masters.com/en/owners/ZipCPU) |
| Stars | 356 |
| Forks | 61 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | GPL-3.0 |
| Created | 2016 |
| Topics | fpga, uart, uart-verilog, verilator, wishbone, wishbone-bus, verilog, serialport |
| Tier | [Alpha (250 to 699 ★)](https://repo.masters-masters.com/en/ranks/b_movie) |
| View on GitHub | [ZipCPU/wbuart32](https://github.com/ZipCPU/wbuart32) |

## Repository

A simple, basic, formally verified UART controller

The tier for repos with 250 to 699 ★. Published odds per card pulled: 20%. Rarity: Uncommon.

## More repos by ZipCPU

- [ZipCPU/zipcpu · ★ 1,597 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ZipCPU/zipcpu)
- [ZipCPU/wb2axip · ★ 714 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ZipCPU/wb2axip)
- [ZipCPU/sdspi · ★ 425 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/ZipCPU/sdspi)
- [ZipCPU/eth10g · ★ 279 · C · Alpha](https://repo.masters-masters.com/en/repos/ZipCPU/eth10g)
- [ZipCPU/dblclockfft · ★ 269 · C++ · Alpha](https://repo.masters-masters.com/en/repos/ZipCPU/dblclockfft)
- [ZipCPU/autofpga · ★ 194 · C++ · Prototype](https://repo.masters-masters.com/en/repos/ZipCPU/autofpga)

## Nearby in Verilog

- [TILOS-AI-Institute/MacroPlacement · ★ 358 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/TILOS-AI-Institute/MacroPlacement)
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- [FPGAwars/icezum · ★ 357 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/FPGAwars/icezum)
- [WangXuan95/FPGA-UART · ★ 354 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-UART)
- [WangXuan95/FPGA-SDcard-Reader · ★ 351 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-SDcard-Reader)
- [WangXuan95/FPGA-JPEG-LS-encoder · ★ 347 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-JPEG-LS-encoder)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.
