# ZipCPU/zipcpu

<https://repo.masters-masters.com/en/repos/ZipCPU/zipcpu>

[Home](https://repo.masters-masters.com/en) › [ZipCPU](https://repo.masters-masters.com/en/owners/ZipCPU) › [zipcpu](https://repo.masters-masters.com/en/repos/ZipCPU/zipcpu)

ZipCPU/zipcpu has 1,597 stars on GitHub. Its RepoMasters card: Beta tier. A small, light weight, RISC CPU soft core Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [ZipCPU](https://repo.masters-masters.com/en/owners/ZipCPU) |
| Stars | 1,597 |
| Forks | 182 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | None |
| Created | 2016 |
| Topics | fpga, soft-core, cross-compiler, verilog, verilator, wishbone, wishbone-bus, zipcpu, cpu, risc-cpu |
| Tier | [Beta (700 to 1,999 ★)](https://repo.masters-masters.com/en/ranks/box_office) |
| View on GitHub | [ZipCPU/zipcpu](https://github.com/ZipCPU/zipcpu) |

## Repository

A small, light weight, RISC CPU soft core

The tier for repos with 700 to 1,999 ★. Published odds per card pulled: 6%. Rarity: Rare.

## More repos by ZipCPU

- [ZipCPU/wb2axip · ★ 713 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ZipCPU/wb2axip)
- [ZipCPU/sdspi · ★ 425 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/ZipCPU/sdspi)
- [ZipCPU/wbuart32 · ★ 356 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/ZipCPU/wbuart32)
- [ZipCPU/eth10g · ★ 279 · C · Alpha](https://repo.masters-masters.com/en/repos/ZipCPU/eth10g)
- [ZipCPU/dblclockfft · ★ 269 · C++ · Alpha](https://repo.masters-masters.com/en/repos/ZipCPU/dblclockfft)
- [ZipCPU/autofpga · ★ 194 · C++ · Prototype](https://repo.masters-masters.com/en/repos/ZipCPU/autofpga)

## Nearby in Verilog

- [ufrisk/pcileech-fpga · ★ 1,848 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ufrisk/pcileech-fpga)
- [ultraembedded/riscv · ★ 1,811 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ultraembedded/riscv)
- [alexforencich/verilog-pcie · ★ 1,675 · Verilog · Beta](https://repo.masters-masters.com/en/repos/alexforencich/verilog-pcie)
- [XUANTIE-RV/openc910 · ★ 1,490 · Verilog · Beta](https://repo.masters-masters.com/en/repos/XUANTIE-RV/openc910)
- [aolofsson/oh · ★ 1,440 · Verilog · Beta](https://repo.masters-masters.com/en/repos/aolofsson/oh)
- [VerticalResearchGroup/miaow · ★ 1,430 · Verilog · Beta](https://repo.masters-masters.com/en/repos/VerticalResearchGroup/miaow)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.
