# abdelazeem201/Systolic-array-implementation-in-RTL-for-TPU

<https://repo.masters-masters.com/en/repos/abdelazeem201/Systolic-array-implementation-in-RTL-for-TPU>

[Home](https://repo.masters-masters.com/en) › [abdelazeem201](https://repo.masters-masters.com/en/owners/abdelazeem201) › [Systolic-array-implementation-in-RTL-for-TPU](https://repo.masters-masters.com/en/repos/abdelazeem201/Systolic-array-implementation-in-RTL-for-TPU)

abdelazeem201/Systolic-array-implementation-in-RTL-for-TPU has 383 stars on GitHub. Its RepoMasters card: Alpha tier. IC implementation of Systolic Array for…

| Field | Value |
| --- | --- |
| Owner | [abdelazeem201](https://repo.masters-masters.com/en/owners/abdelazeem201) |
| Stars | 383 |
| Forks | 39 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | MIT |
| Created | 2021 |
| Topics | asic, asic-design, asic-verification, fpga, rtl, verilog |
| Tier | [Alpha (250 to 699 ★)](https://repo.masters-masters.com/en/ranks/b_movie) |
| View on GitHub | [abdelazeem201/Systolic-array-implementation-in-RTL-for-TPU](https://github.com/abdelazeem201/Systolic-array-implementation-in-RTL-for-TPU) |

## Repository

IC implementation of Systolic Array for TPU

The tier for repos with 250 to 699 ★. Published odds per card pulled: 20%. Rarity: Uncommon.

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.