# agg23/openfpga-NES

<https://repo.masters-masters.com/en/repos/agg23/openfpga-NES>

[Home](https://repo.masters-masters.com/en) › [agg23](https://repo.masters-masters.com/en/owners/agg23) › [openfpga-NES](https://repo.masters-masters.com/en/repos/agg23/openfpga-NES)

agg23/openfpga-NES has 224 stars on GitHub. Its RepoMasters card: Prototype tier. NES for the Analogue Pocket Language: SystemVerilog.

| Field | Value |
| --- | --- |
| Owner | [agg23](https://repo.masters-masters.com/en/owners/agg23) |
| Stars | 224 |
| Forks | 15 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | GPL-3.0 |
| Created | 2022 |
| Topics | analogue-pocket, fpga, nes, openfpga |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [agg23/openfpga-NES](https://github.com/agg23/openfpga-NES) |

## Repository

NES for the Analogue Pocket

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by agg23

- [agg23/openfpga-SNES · ★ 448 · VHDL · Alpha](https://repo.masters-masters.com/en/repos/agg23/openfpga-SNES)
- [agg23/fpga-tamagotchi · ★ 178 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/agg23/fpga-tamagotchi)
- [agg23/analogue-pocket-utils · ★ 127 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/agg23/analogue-pocket-utils)

## Nearby in SystemVerilog

- [pulp-platform/snitch · ★ 229 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/pulp-platform/snitch)
- [svunit/svunit · ★ 227 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/svunit/svunit)
- [subbdue/systemverilog.io · ★ 226 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/subbdue/systemverilog.io)
- [taichi-ishitani/tnoc · ★ 216 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/taichi-ishitani/tnoc)
- [tilk/riscv-simple-sv · ★ 216 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/tilk/riscv-simple-sv)
- [openhwfoundation/core-v-mcu · ★ 215 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/openhwfoundation/core-v-mcu)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.