# alexforencich/verilog-axi

<https://repo.masters-masters.com/en/repos/alexforencich/verilog-axi>

[Home](https://repo.masters-masters.com/en) › [alexforencich](https://repo.masters-masters.com/en/owners/alexforencich) › [verilog-axi](https://repo.masters-masters.com/en/repos/alexforencich/verilog-axi)

alexforencich/verilog-axi has 2,168 stars on GitHub. Its RepoMasters card: RC tier. Verilog AXI components for FPGA implementation Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [alexforencich](https://repo.masters-masters.com/en/owners/alexforencich) |
| Stars | 2,168 |
| Forks | 546 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | MIT |
| Created | 2018 |
| Tier | [RC (2,000 to 4,999 ★)](https://repo.masters-masters.com/en/ranks/blockbuster) |
| View on GitHub | [alexforencich/verilog-axi](https://github.com/alexforencich/verilog-axi) |

## Repository

Verilog AXI components for FPGA implementation

The tier for repos with 2,000 to 4,999 ★. Published odds per card pulled: 3%. Rarity: Epic.

## More repos by alexforencich

- [alexforencich/verilog-ethernet · ★ 3,145 · Verilog · RC](https://repo.masters-masters.com/en/repos/alexforencich/verilog-ethernet)
- [alexforencich/verilog-pcie · ★ 1,675 · Verilog · Beta](https://repo.masters-masters.com/en/repos/alexforencich/verilog-pcie)
- [alexforencich/verilog-axis · ★ 925 · Python · Beta](https://repo.masters-masters.com/en/repos/alexforencich/verilog-axis)
- [alexforencich/verilog-i2c · ★ 731 · Verilog · Beta](https://repo.masters-masters.com/en/repos/alexforencich/verilog-i2c)
- [alexforencich/verilog-uart · ★ 591 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/alexforencich/verilog-uart)
- [alexforencich/cocotbext-axi · ★ 368 · Python · Alpha](https://repo.masters-masters.com/en/repos/alexforencich/cocotbext-axi)

## Nearby in Verilog

- [corundum/corundum · ★ 2,505 · Verilog · RC](https://repo.masters-masters.com/en/repos/corundum/corundum)
- [vortexgpgpu/vortex · ★ 2,378 · Verilog · RC](https://repo.masters-masters.com/en/repos/vortexgpgpu/vortex)
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- [XUANTIE-RV/wujian100\_open · ★ 2,032 · Verilog · RC](https://repo.masters-masters.com/en/repos/XUANTIE-RV/wujian100_open)
- [pConst/basic\_verilog · ★ 2,029 · Verilog · RC](https://repo.masters-masters.com/en/repos/pConst/basic_verilog)
- [riscv-mcu/e203\_hbirdv2 · ★ 1,973 · Verilog · Beta](https://repo.masters-masters.com/en/repos/riscv-mcu/e203_hbirdv2)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.