# alexforencich/verilog-axis

<https://repo.masters-masters.com/en/repos/alexforencich/verilog-axis>

[Home](https://repo.masters-masters.com/en) › [alexforencich](https://repo.masters-masters.com/en/owners/alexforencich) › [verilog-axis](https://repo.masters-masters.com/en/repos/alexforencich/verilog-axis)

alexforencich/verilog-axis has 925 stars on GitHub. Its RepoMasters card: Beta tier. Verilog AXI stream components for FPGA implementation Language: Python.

| Field | Value |
| --- | --- |
| Owner | [alexforencich](https://repo.masters-masters.com/en/owners/alexforencich) |
| Stars | 925 |
| Forks | 279 |
| Language | [Python](https://repo.masters-masters.com/en/languages/python) |
| License | MIT |
| Created | 2014 |
| Tier | [Beta (700 to 1,999 ★)](https://repo.masters-masters.com/en/ranks/box_office) |
| View on GitHub | [alexforencich/verilog-axis](https://github.com/alexforencich/verilog-axis) |

## Repository

Verilog AXI stream components for FPGA implementation

The tier for repos with 700 to 1,999 ★. Published odds per card pulled: 6%. Rarity: Rare.

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.