# alexforencich/verilog-dsp

<https://repo.masters-masters.com/en/repos/alexforencich/verilog-dsp>

[Home](https://repo.masters-masters.com/en) › [alexforencich](https://repo.masters-masters.com/en/owners/alexforencich) › [verilog-dsp](https://repo.masters-masters.com/en/repos/alexforencich/verilog-dsp)

alexforencich/verilog-dsp has 197 stars on GitHub. Its RepoMasters card: Prototype tier. Verilog digital signal processing components Language: Python.

| Field | Value |
| --- | --- |
| Owner | [alexforencich](https://repo.masters-masters.com/en/owners/alexforencich) |
| Stars | 197 |
| Forks | 40 |
| Language | [Python](https://repo.masters-masters.com/en/languages/python) |
| License | MIT |
| Created | 2015 |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [alexforencich/verilog-dsp](https://github.com/alexforencich/verilog-dsp) |

## Repository

Verilog digital signal processing components

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.